1) Field of the Invention
Embodiments of the present invention relate to a data strobe control device, and more particularly to a technology for controlling a data write path of a semiconductor memory device.
2) Description of the Related Art
With the increasing degree of integration of semiconductor memory devices, semiconductor memory devices have been continuously improved to increase operation speed. In order to increase operation speed, synchronous memory devices capable of operating by synchronizing with an external clock of a memory chip have recently been proposed and developed.
A representative example of a synchronous memory device is a single data rate (SDR) synchronous memory device that is synchronized with a rising edge of an external clock of a memory device such that one data piece can be input and/or output during one clock period at one data pin.
However, the SDR synchronous memory device also has difficulty in satisfying high-speed operations of a system. Thus, a double data rate (DDR) synchronous memory device capable of processing two data pieces during one clock period has been proposed.
Two contiguous data pieces are input and output through respective data input/output (I/O) pins of a DDR synchronous memory device, such that the two contiguous data pieces are synchronized with a rising edge and a falling edge of an external input clock. Therefore, although the clock frequency of a DDR synchronous memory device is not increased, the DDR synchronous memory device may have a bandwidth that is at least two times larger than that of an SDR synchronous memory device, such that a DDR synchronous memory device can operate at a higher speed than an SDR synchronous memory device.
The DDR synchronous memory device is configured to use a multi-bit prefetching scheme capable of simultaneously processing multiple bits (multi-bit). The multi-bit prefetch scheme synchronizes sequential input data pieces with a data strobe signal such that the input data pieces can be arranged in parallel to one another. Thereafter, a multi-bit prefetch scheme can simultaneously store the arranged multi-bit data pieces upon receiving a write command synchronized with an external clock signal.
Meanwhile, an operation mode for supporting a 2-clock base operation between different bank groups is referred to as a plus mode. If a DDR synchronous memory device enters the plus mode, the DDR synchronous memory device performs a normal 4-clock write/read operation on the basis of DDR3, and then performs a 2-clock write/read operation.
Specifically, the plus mode is also applied to an on-the-fly mode. The on-the-fly mode is a specific mode in which a burst length BL4 or a burst length BL8 is carried out based on an address. As can be seen from the JEDEC specification, a bank is largely divided into two bank parts in a manner that all cells contained in a memory bank can be utilized either in the burst length BL4 or in the on-the-fly mode operation, such that a selection operation for determining whether data will be written at the left or right side is achieved.
In this case, during a normal on-the-fly mode, a 4-clock base operation is achieved so that an address variation occurs in the range of 4 clocks. However, a clock base operation is needed for the plus on-the-fly mode, such that a normal operation must be performed by an on-the-fly-associated address toggle action. In the case of a manufactured product configured to operate at a low power-supply voltage, a defective margin frequently occurs between an address and an operation command.